The present application may relate to co-pending application Ser. No. 09/714,441, filed Nov. 16, 2000, Ser. No. 09/732,685, now U.S. Pat. No. 6,629,226 Ser. No. 09/732,687, now U.S. Pat. No. 6,715,021 Ser. No. 09/676,704, filed Sep. 29, 2000, Ser. No. 09/676,171, filed Sep. 29, 2000, now U.S. Pat. No. 6,578,118, Ser. No. 09/676,706, filed Sep. 29, 2000, Ser. No. 09/676,705, filed Sep. 29, 2000, now U.S. Pat. No. 6,631,455, Ser. No. 09/676,170, filed Sep. 29, 2000, now U.S. Pat. No. 6,581,144, and Ser. No. 09/676,169, filed Sep. 29, 2000, which are each hereby incorporated by reference in their entirety.
The present invention relates to a method and/or architecture for implementing a multiqueue first-in-first-out (FIFO) memory read interface generally and, more particularly, to a method and/or architecture for implementing a multiqueue FIFO read interface protocol for eliminating synchronizing problems for configuration dependent latencies where the protocol may be capable of handling variable size packets.
The present invention may also relate to a method and/or architecture for variable stage pipeline system generally and, more particularly, to a method and/or architecture for implementing an event driven variable stage pipeline system for handling variable size blocks that may have a minimum block size less than total round-time delay.
Referring to FIG. 1, a diagram illustrating a conventional circuit 10 for exchanging data between a first-in-first-out (FIFO) device 12 and a read device 14 is shown. A read signal RD is presented from the read device 14 to the FIFO 12. After a fixed number of latency cycles, the signal DATA is presented to the read device 14. The signals READ_CLOCK and RD control the timing of the presentation of the data signal DATA.
Referring to FIG. 2, a diagram illustrating a conventional system 30 for exchanging data between a multiqueue FIFO 32 and a read device 34 is shown. The signal ADDRESS is a queue address configured to determine a queue number of the multiqueue FIFO 32. The signals READ_CLOCK and READ_EN control the timing of the presentation of the data signal DATA.
The read signal_RD in FIG. 1 is replaced by the read enable signal READ_EN in FIG. 2. The signal READ_EN controls whether to continue or to stop a particular read. The queue address signal ADDRESS is an additional signal not present in FIG. 1. Since there are multiple queues in the FIFO 32, a read occurs from the particular queue that is addressed by the signal ADDRESS.
Because of particular architectures (e.g., the cited co-pending applications) and specifications of particular devices, the latency between enabling the queue address signal ADDRESS and presenting the signal DATA can differ depending on the particular configuration. The configuration information needs to be written into the external read device 34. The only event reference available to the external read device 34 is an end of packet or a start of packet (EOP/SOP). In such an environment, the read device 34 is required to monitor this event to generate the queue address signal ADDRESS in a sufficient number of cycles ahead of the read.
The circuit 30 has the disadvantage of requiring a fixed packet size. The circuit 30 can be required to generate the queue address ADDRESS a certain number of cycles before the EOP occurs. The particular number of cycles is the same as the minimum latency requirement. For certain configurations, there is a specific latency between the queue address signal ADDRESS and presenting the signal DATA. If the packet size varies randomly, such as when the size of the packet is less than the number of cycles of latency, a read of one or more unwanted packets occurs. The circuit 30 additionally requires a pipeline memory (within the multiqueue 32) to handle variable sized packets in an asynchronous configuration.
It may also be difficult for the read device 34 to synchronize the queue address signal ADDRESS with the data received from the FIFO 32. Therefore, the read device 34 needs to be configured with enough logic to respond to the different latencies. Such a configuration requires extra overhead for the read device 34.
Handling of slow read clock speeds is also difficult within the circuit 30. The read operation occurs at one clock and the internal logic operates at another clock, such as the system clock (e.g., the cited co-pending application). This requires the queue address signal ADDRESS and the read enable signal READ_EN to be synchronized before other processing can be executed. The data read also needs to be synchronized. As a result, there is an uncertainty of 1-2 clock cycles resulting in the latency. This makes the synchronization between the queue address signal ADDRESS and the data read extremely difficult.
One aspect of the present invention concerns an interface coupled to a multiqueue storage device and configured to interface the multiqueue storage device with one or more handshaking signals. The multiqueue storage device and the interface may be configured to transfer variable size data packets.
Another aspect of the present invention concerns an apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a multiqueue FIFO read interface protocol that may (i) eliminate synchronizing problems with configuration dependent latencies; (ii) be capable of handling variable size packets; (iii) allow back-to-back reads of variable size packets; (iv) exchange address and data between an external read device and a multiqueue storage device; (v) generate an address request for an external device from the storage device; (vi) generate a valid queue address in response to the address request; (vii) provide data in response to the valid queue address; (viii) provide a single clock domain or a dual clock domain between a multiqueue storage device and a read interface device; (ix) vary a latency between an address request and an address validate; (x) provide an event driven variable stage pipeline system; and/or (xi) handle variable size packets with a minimum packet size less than a total round-time delay.